For example, in the conventional Group III nitride semiconductor light-emitting device, even when a p-type layer is subjected to a treatment for reducing a resistivity, the p-type layer is higher in resistivity than an n-type layer. Therefore, light emits only right under the electrode because the current does not substantially diffuse in a lateral direction on a plane within the p-type layer. Thus, it is necessary that an electrode layer must be formed over a wide range on the upper surface of the p-type layer. Also, it is necessary that an electrode for the n-type layer as a lower layer is formed on the upper surface of the device because an insulating material such as sapphire is used as a substrate. In order to achieve this, there was a need to remove the p-type layer, the light-emitting layer and so on existing above the n-type layer by etching to expose a portion of the n-type layer being an n-electrode forming part, to form the electrode on the upper surface of the exposed n-type layer, and to form a transparent electrode on the upper surface of the p-type layer.
As described above, the exposure process of the n-type layer, the formation process of the n-electrode on the n-type layer, the formation process of a transparent electrode on the p-type layer, a plurality of photolisography processes and the etching process were required. Since the transparent electrode is formed on the p-type layer after the exposure process of the n-type layer, it is difficult to form a mask having windows formed on an entire top surface of the p-type layer, with accurate positioning at a boundary between the exposed n-type layer and the p-type layer. Accordingly, the transparent electrode had to be formed on the p-type layer about a few μm back from the above boundary (i.e., the edge of the step). Thus, there is a portion of the p-type layer on which the transparent electrode is not formed, that is, there is a portion that does not contribute to light emission, resulting in a reduction of light emission efficiency.
To solve this problem, the technologies disclosed in the following Patent Documents 1 and 2 are available. In the technology of Patent Document 1, after a transparent electrode made of metal and a SiO2 layer are formed on an entire top surface of a p-type layer, a photo-resist is applied on an entire top surface of the SiO2 layer. A portion, which corresponds to a portion to expose the n-type layer, of the SiO2 layer is wet etched by photolisography. Semiconductor layers such as a p-type layer are dry etched using the remaining photo-resist and the SiO2 layer as a mask, to expose the portion of the n-type layer, and the SiO2 layer is removed by wet etching. This process can improve light emission efficiency because the transparent electrode is formed up to a boundary between the exposed n-type layer and p-type layer as well as the total number of processes is reduced. However, conductive atoms such as metal are adhered to a pn junction on the sidewall of the step in the process for exposing the n-type layer, and thus the reliability of the device was reduced.
On the other hand, the technology disclosed in the Patent Document 2 uses ITO as a transparent electrode on a p-type layer. In this technology, after an ITO transparent electrode is formed on an entire top surface of the p-type layer, a photo-resist is applied thereon, and a portion, which corresponds to a portion to expose the n-type layer, of the ITO film is wet etched by photolisography. Semiconductor layers such as p-type layer are dry etched using the remaining photo-resist and the ITO film as mask, to expose the portion of the n-type layer. Moreover, when an electric field is applied to the p-type layer edge of the etched step, electrostatic break down voltage is reduced. To prevent the electric field from being applied to the p-type layer edge, an ITO film is formed in a position of about 3 μm backward from the p-type layer edge. Therefore, when the ITO film is wet etched using a mask, the ITO film is undercut etched from the mask edge to the position backward from the mask edge. This makes the ITO film edge position in a position backward from the edge of the p-type layer so that an electric field is not applied to the p-type layer edge of the step.